| A non-volatile microcontroller with integrated floating-gate transistors W Yu, S Rajwade, SE Wang, B Lian, GE Suh, E Kan 2011 IEEE/IFIP 41st International Conference on Dependable Systems and …, 2011 | 66 | 2011 |
| EC-AFM investigation of reversible volume changes with electrode potential in polyaniline PR Singh, S Mahajan, S Rajwade, AQ Contractor Journal of Electroanalytical Chemistry 625 (1), 16-26, 2009 | 46 | 2009 |
| Integration of self-assembled redox molecules in flash memory devices J Shaw, YW Zhong, KJ Hughes, TH Hou, H Raza, S Rajwade, J Bellfy, ... IEEE transactions on electron devices 58 (3), 826-834, 2010 | 42 | 2010 |
| 30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density A Khakifirooz, S Balasubrahmanyam, R Fastow, KH Gaewsky, CW Ha, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 424-426, 2021 | 38 | 2021 |
| Programmable ion-sensitive transistor interfaces. II. Biomolecular sensing and manipulation K Jayant, K Auluck, M Funke, S Anwar, JB Phelps, PH Gordon, ... Physical Review E 88 (1), 012802, 2013 | 38 | 2013 |
| Programmable ion-sensitive transistor interfaces. I. Electrochemical gating K Jayant, K Auluck, M Funke, S Anwar, JB Phelps, PH Gordon, ... Physical Review E 88 (1), 012801, 2013 | 31 | 2013 |
| Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation SR Rajwade, P Kalavade, T Tanzawa US Patent 9,910,594, 2018 | 24 | 2018 |
| Method and apparatus for protecting lower page data during programming in NAND flash SR Rajwade, P Kalavade US Patent 9,703,494, 2017 | 17 | 2017 |
| A ferroelectric and charge hybrid nonvolatile memory—Part II: Experimental validation and analysis SR Rajwade, K Auluck, JB Phelps, KG Lyon, JT Shaw, EC Kan IEEE transactions on electron devices 59 (2), 450-458, 2011 | 11 | 2011 |
| A ferroelectric and charge hybrid nonvolatile memory—Part I: Device concept and modeling SR Rajwade, K Auluck, JB Phelps, KG Lyon, JT Shaw, EC Kan IEEE transactions on electron devices 59 (2), 441-449, 2011 | 11 | 2011 |
| A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3 Gb/mm2 Bit Density A Khakifirooz, E Anaya, S Balasubrahmanyam, G Bennett, D Castro, ... IEEE Solid-State Circuits Letters, 2023 | 9 | 2023 |
| Segmented erase in memory SR Rajwade, A Goda, P Kalavade, KK Parat, H Sanda US Patent 10,453,535, 2019 | 8 | 2019 |
| Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation SR Rajwade, P Kalavade, T Tanzawa US Patent 10,379,738, 2019 | 8 | 2019 |
| Ferroelectric-assisted dual-switching speed DRAM–flash hybrid memory SR Rajwade, TA Naoi, K Auluck, K Jayant, RB Van Dover, EC Kan IEEE transactions on electron devices 60 (6), 1944-1950, 2013 | 8 | 2013 |
| Redox molecules for a resonant tunneling barrier in nonvolatile memory J Shaw, Q Xu, S Rajwade, TH Hou, EC Kan IEEE transactions on electron devices 59 (4), 1189-1198, 2012 | 8 | 2012 |
| Predictive count fail byte (CFBYTE) for non-volatile memory SR Rajwade, P Kalavade US Patent 10,141,071, 2018 | 7 | 2018 |
| Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation SR Rajwade, P Kalavade, T Tanzawa US Patent 11,182,074, 2021 | 6 | 2021 |
| Method and apparatus for dynamically determining start program voltages for a memory device PS Sule, AS Madraswala, SR Rajwade, TR Bemalkhedkar, LA Turcios, ... US Patent 10,224,107, 2019 | 6 | 2019 |
| Method and apparatus for reducing data program completion overhead in NAND flash SR Rajwade, A D'alessandro, P Kalavade, V Moschiano US Patent 9,852,065, 2017 | 6 | 2017 |
| Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash S Rajwade, W Yu, S Xu, TH Hou, GE Suh, E Kan 23rd IEEE International SOC Conference, 461-466, 2010 | 6 | 2010 |
