| Using a single input to support multiple scan chains KJ Lee, JJ Chen, CH Huang Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 251 | 1998 |
| Peak-power reduction for multiple-scan circuits during test application KJ Lee, TC Haung, JJ Chen Proceedings of the Ninth Asian Test Symposium, 453-458, 2000 | 91 | 2000 |
| A novel test methodology based on error-rate to support error-tolerance KJ Lee, TY Hsieh, MA Breuer IEEE International Conference on Test, 2005., 9 pp.-1144, 2005 | 89 | 2005 |
| Broadcasting test patterns to multiple circuits KJ Lee, JJ Chen, CH Huang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999 | 89 | 1999 |
| A practical current sensing technique for I/sub DDQ/testing JJ Tang, KJ Lee, BD Liu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (2), 302-310, 1995 | 80 | 1995 |
| Test power reduction with multiple capture orders KJ Lee, SJ Hsu, CM Ho 13th Asian Test Symposium, 26-31, 2004 | 71 | 2004 |
| Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults KJ Lee, MA Breuer IEEE transactions on computer-aided design of integrated circuits and …, 1992 | 70 | 1992 |
| An on chip ADC test structure YC Wen, KJ Lee Proceedings of the conference on Design, automation and test in Europe, 221-225, 2000 | 62 | 2000 |
| Reduction of power consumption in scan-based circuits during test application by an input control technique TC Huang, KJ Lee IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001 | 60 | 2001 |
| An input control technique for power reduction in scan circuits during test application TC Huang, KJ Lee Proceedings Eighth Asian Test Symposium (ATS'99), 315-320, 1999 | 56 | 1999 |
| A token scan architecture for low power testing TC Huang, KJ Lee Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 660-669, 2001 | 55 | 2001 |
| A universal test sequence for CMOS scan registers KJ Lee, MA Breuer IEEE Proceedings of the Custom Integrated Circuits Conference, 28.5/1-28.5/4, 1990 | 47 | 1990 |
| Effective hybrid test program development for software-based self-testing of pipeline processor cores TH Lu, CH Chen, KJ Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (3), 516-520, 2009 | 46 | 2009 |
| Reduction of detected acceptable faults for yield improvement via error-tolerance TY Hsieh, KJ Lee, MA Breuer 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 44 | 2007 |
| An on-chip march pattern generator for testing embedded memory cores WL Wang, KJ Lee, JF Wang IEEE transactions on very large scale integration (VLSI) systems 9 (5), 730-735, 2001 | 44 | 2001 |
| A hierarchical test control architecture for core based design KJ Lee, CI Huang Proceedings of the Ninth Asian Test Symposium, 248-253, 2000 | 41 | 2000 |
| A current-mode testable design of operational transconductance amplifier-capacitor filters KJ Lee, WC Wang, KS Huang IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1999 | 41 | 1999 |
| Tolerance of performance degrading faults for effective yield improvement TY Hsieh, MA Breuer, M Annavaram, SK Gupta, KJ Lee 2009 International Test Conference, 1-10, 2009 | 36 | 2009 |
| On the charge sharing problem in CMOS stuck-open fault testing KJ Lee, MA Breuer Proceedings. International Test Conference 1990, 417-426, 1990 | 36 | 1990 |
| An embedded processor based SOC test platform KJ Lee, CY Chu, YT Hong 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2983-2986, 2005 | 34 | 2005 |
