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Tung-Chieh Chen
Tung-Chieh Chen
Maxeda Technology
Verified email at eda.ee.ntu.edu.tw
Title
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Cited by
Year
NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints
TC Chen, ZW Jiang, TC Hsu, HC Chen, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
3342008
Modern floorplanning based on B/sup*/-tree and fast simulated annealing
TC Chen, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1772006
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
TC Chen, ZW Jiang, TC Hsu, HC Chen, YW Chang
Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided …, 2006
992006
Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio
F Chang, S Chen, T Chen, R Tsay, WK Mak
US Patent 8,407,647, 2013
922013
Modern floorplanning based on fast simulated annealing
TC Chen, YW Chang
Proceedings of the 2005 international symposium on Physical design, 104-112, 2005
912005
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
TC Chen, TC Hsu, ZW Jiang, YW Chang
Proceedings of the 2005 international symposium on Physical design, 236-238, 2005
832005
NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs
MK Hsu, YF Chen, CC Huang, S Chou, TH Lin, TC Chen, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
682014
MP-trees: a packing-based macro placement algorithm for mixed-size designs
TC Chen, PH Yuh, YW Chang, FJ Huang, D Liu
Design Automation Conference, 2007. DAC'07. 44th ACM/IEEE, 447-452, 2007
682007
IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs
TC Chen, YW Chang, SC Lin
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
552005
Essential issues in analytical placement algorithms
YW Chang, ZW Jiang, TC Chen
IPSJ Transactions on System LSI Design Methodology 2, 145-166, 2009
532009
NTUplace4dr: a detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints
CC Huang, HY Lee, BQ Lin, SW Yang, CH Chang, ST Chen, YW Chang, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
522017
A novel analog physical synthesis methodology integrating existent design expertise
PH Wu, MPH Lin, TC Chen, CF Yeh, X Li, TY Ho
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
512014
A new multilevel framework for large-scale interconnect-driven floorplanning
TC Chen, YW Chang, SC Lin
IEEE transactions on computer-aided design of integrated circuits and …, 2008
502008
Fast analog layout prototyping for nanometer design migration
YP Weng, HM Chen, TC Chen, PC Pan, CH Chen, WZ Chen
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 517-522, 2011
432011
NTUplace2: A hybrid placer using partitioning and analytical techniques
ZW Jiang, TC Cheny, TC Hsuy, HC Chenz, YW Changyz
Proceedings of the 2006 international symposium on Physical design, 215-217, 2006
432006
Routability-driven placement for hierarchical mixed-size circuit designs
MK Hsu, YF Chen, CC Huang, TC Chen, YW Chang
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
362013
Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement
PH Wu, MPH Lin, TC Chen, CF Yeh, TY Ho, BD Liu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
322014
Performance-driven analog placement considering monotonic current paths
PH Wu, MPH Lin, YR Chen, BS Chou, TC Chen, TY Ho, BD Liu
Proceedings of the International Conference on Computer-Aided Design, 613-619, 2012
302012
Metal-density-driven placement for CMP variation and routability
TC Chen, M Cho, DZ Pan, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
292008
Analytical global placement for an integrated circuit
T Chen, C Jiang
US Patent App. 12/168,288, 2009
282009
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Articles 1–20