| Multi-layer sidewall WOX resistive memory suitable for 3D ReRAM WC Chien, FM Lee, YY Lin, MH Lee, SH Chen, CC Hsieh, EK Lai, HH Hui, ... 2012 Symposium on VLSI technology (VLSIT), 153-154, 2012 | 70 | 2012 |
| Radically extending the cycling endurance of Flash memory (to> 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage HT Lue, PY Du, CP Chen, WC Chen, CC Hsieh, YH Hsiao, YH Shih, ... 2012 International Electron Devices Meeting, 9.1. 1-9.1. 4, 2012 | 60 | 2012 |
| Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash CP Chen, HT Lue, CC Hsieh, KP Chang, KY Hsieh, CY Lu 2010 International Electron Devices Meeting, 5.6. 1-5.6. 4, 2010 | 60 | 2010 |
| A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL) CP Chen, HT Lue, KP Chang, YH Hsiao, CC Hsieh, SH Chen, YH Shih, ... 2012 Symposium on VLSI Technology (VLSIT), 91-92, 2012 | 48 | 2012 |
| A highly scalable 8-layer vertical gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (minimal incremental layer cost) staircase contacts SH Chen, HT Lue, YH Shih, CF Chen, TH Hsu, YR Chen, YH Hsiao, ... 2012 International Electron Devices Meeting, 2.3. 1-2.3. 4, 2012 | 41 | 2012 |
| Programming multibit memory cells CC Hsieh, TW Chen, YC Li, KP Chang US Patent 9,685,233, 2017 | 32 | 2017 |
| Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application TH Hsu, HT Lue, CC Hsieh, EK Lai, CP Lu, SP Hong, MT Wu, FH Hsu, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 32 | 2009 |
| A 128Gb (MLC)/192Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability HT Lue, PY Du, WC Chen, YC Lee, TH Hsu, TH Yeh, KP Chang, ... 2017 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2017 | 30 | 2017 |
| A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity HT Lue, TH Hsu, CJ Wu, WC Chen, TH Yeh, KP Chang, CC Hsieh, PY Du, ... 2015 IEEE International Electron Devices Meeting (IEDM), 3.2. 1-3.2. 4, 2015 | 27 | 2015 |
| Thermally assisted dielectric charge trapping flash HT Lue, CP Chen, CC Hsieh, YH Hsiao US Patent 8,488,387, 2013 | 22 | 2013 |
| Memory architecture of 3d vertical gate (3dvg) nand flash using plural island-gate ssl decoding method and study of it's program inhibit characteristics KP Chang, HT Lue, CP Chen, CF Chen, YR Chen, YH Hsiao, CC Hsieh, ... 2012 4th IEEE International Memory Workshop, 1-4, 2012 | 21 | 2012 |
| A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip CC Hsieh, HT Lue, TH Hsu, PY Du, KH Chiang, CY Lu 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 19 | 2016 |
| High-aspect ratio through silicon via (TSV) technology HB Chang, HY Chen, PC Kuo, CH Chien, EB Liao, TC Lin, TS Wei, YC Lin, ... 2012 Symposium on VLSI Technology (VLSIT), 173-174, 2012 | 19 | 2012 |
| NAND flash biasing operation TW Chen, HT Lue, SN Hung, SL Huang, CC Hsieh, KP Chang US Patent 8,760,928, 2014 | 17 | 2014 |
| Programming technique for reducing program disturb in stacked memory structures SN Hung, HT Lue, TW Chen, SL Huang, KP Chang, CC Hsieh, CH Hung US Patent App. 13/827,475, 2014 | 16 | 2014 |
| Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage CC Hsieh, HT Lue, YC Li, KP Chang, HC Lu, HP Li, WC Chen, YH Hsiao, ... 2013 Symposium on VLSI Technology, T156-T157, 2013 | 16 | 2013 |
| Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash WC Chen, HT Lue, KP Chang, YH Hsiao, CC Hsieh, YH Shih, CY Lu Proceedings of Technical Program-2014 International Symposium on VLSI …, 2014 | 15 | 2014 |
| In-memory-searching architecture based on 3D-NAND technology with ultra-high parallelism PH Tseng, FM Lee, YH Lin, LY Chen, YC Li, HW Hu, YY Wang, CC Hsieh, ... 2020 IEEE International Electron Devices Meeting (IEDM), 36.1. 1-36.1. 4, 2020 | 14 | 2020 |
| Device characteristics of single-gate vertical channel (SGVC) 3D NAND flash architecture CJ Wu, HT Lue, TH Hsu, CC Hsieh, WC Chen, PY Du, CJ Chiu, CY Lu 2016 IEEE 8th International Memory Workshop (IMW), 1-4, 2016 | 14 | 2016 |
| A physics-based Quasi-2D model to understand the wordline (WL) interference effects of junction-free structure of 3D NAND and experimental study in a 3D NAND flash test chip WC Chen, HT Lue, CC Hsieh, YC Lee, PY Du, TH Hsu, KP Chang, ... 2017 IEEE International Electron Devices Meeting (IEDM), 4.6. 1-4.6. 4, 2017 | 13 | 2017 |
