| A novel analog physical synthesis methodology integrating existent design expertise PH Wu, MPH Lin, TC Chen, CF Yeh, X Li, TY Ho IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 51 | 2014 |
| Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement PH Wu, MPH Lin, TC Chen, CF Yeh, TY Ho, BD Liu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 32 | 2014 |
| Performance-driven analog placement considering monotonic current paths PH Wu, MPH Lin, YR Chen, BS Chou, TC Chen, TY Ho, BD Liu Proceedings of the International Conference on Computer-Aided Design, 613-619, 2012 | 30 | 2012 |
| Analog layout synthesis with knowledge mining PH Wu, MPH Lin, TY Ho 2015 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2015 | 28 | 2015 |
| 1-D cell generation with printability enhancement PH Wu, MPH Lin, TC Chen, TY Ho, YC Chen, SR Siao, SH Lin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 21 | 2013 |
| Knowledge-based analog layout generator TC Chen, PH Wu, PH Lin, TY Ho US Patent 9,256,706, 2016 | 12 | 2016 |
| Bus-driven floorplanning with thermal consideration PH Wu, TY Ho Integration 46 (4), 369-381, 2013 | 8 | 2013 |
| A topology-based eco routing methodology for mask cost minimization PH Wu, SY Bai, TY Ho 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 507-512, 2014 | 7 | 2014 |
| Parasitic-aware common-centroid FinFET placement and routing for current-ratio matching PH Wu, MPH Lin, X Li, TY Ho ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (3 …, 2016 | 6 | 2016 |
| Common-centroid FinFET placement considering the impact of gate misalignment PH Wu, MPH Lin, X Li, TY Ho Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015 | 5 | 2015 |
| Placement optimization of flexible TFT circuits with mechanical strain and temperature consideration JL Lin, PH Wu, TY Ho ACM Journal on Emerging Technologies in Computing Systems (JETC) 11 (1), 1-28, 2014 | 5 | 2014 |
| A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration JL Lin, PH Wu, TY Ho 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 491-496, 2013 | 5 | 2013 |
| Triangle-based process hotspot classification with dummification in EUVL PH Wu, CW Chen, CR Wu, TY Ho Technical Papers of 2014 International Symposium on VLSI Design, Automation …, 2014 | 4 | 2014 |
| Thermal-aware bus-driven floorplanning PH Wu, TY Ho IEEE/ACM International Symposium on Low Power Electronics and Design, 205-210, 2011 | 4 | 2011 |
| Bus-driven floorplanning with bus pin assignment and deviation minimization PH Wu, TY Ho Integration 45 (4), 405-426, 2012 | 3 | 2012 |
| Knowledge-based analog layout generator TC Chen, PH Wu, PH Lin, TY Ho US Patent 11,010,528, 2021 | 1 | 2021 |
| Lithography-aware 1-dimensional cell generation PH Wu, MPH Lin, TC Chen, TY Ho, YC Chen 2013 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2013 | | 2013 |
