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Meng-Kai Hsu
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Cited by
Year
Method of analytical placement with weighted-average wirelength model
V Balabanov, MK Hsu, YW Chang
US Patent 8,689,164, 2014
2382014
TSV-aware analytical placement for 3D IC designs
MK Hsu, YW Chang, V Balabanov
Proceedings of the 48th Design Automation Conference, 664-669, 2011
1192011
TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model
MK Hsu, V Balabanov, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
922013
Routability-driven analytical placement for mixed-size circuit designs
MK Hsu, S Chou, TH Lin, YW Chang
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 80-84, 2011
882011
NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs
MK Hsu, YF Chen, CC Huang, S Chou, TH Lin, TC Chen, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
682014
Design and manufacturing process co-optimization in nano-technology (Designer Track Paper)
MK Hsu, N Katta, HYH Lin, KTH Lin, KH Tam, KCH Wang
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 574-581, 2014
412014
Structure-aware placement for datapath-intensive circuit designs
S Chou, MK Hsu, YW Chang
Proceedings of the 49th Annual Design Automation Conference, 762-767, 2012
392012
Unified analytical global placement for large-scale mixed-size circuit designs
MK Hsu, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
372012
Routability-driven placement for hierarchical mixed-size circuit designs
MK Hsu, YF Chen, CC Huang, TC Chen, YW Chang
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
362013
Spare-cell-aware multilevel analytical placement
ZW Jiang, MK Hsu, YW Chang, KY Chao
Proceedings of the 46th Annual Design Automation Conference, 430-435, 2009
102009
Method for triple-patterning friendly placement
MK Hsu, YT Hou, WH Chen
US Patent 10,089,433, 2018
92018
Rule checking for multiple patterning technology
MK Hsu, YT Hou, WH Chen
US Patent 9,971,863, 2018
82018
Generating database for cells routable in pin layer
MK Hsu, CY Yu, YT Hou, WH Chen
US Patent 9,064,081, 2015
82015
Systems and methods for using multiple libraries with different cell pre-coloring
MK Hsu, YT Hou, WH Chen
US Patent 10,162,929, 2018
52018
Rule checking for confining waveform induced constraint variation in static timing analysis
MK Hsu, WH Chen
US Patent 9,165,105, 2015
52015
Method and system of revising a layout diagram
MK Hsu, SH Chen, WK Mak, TC Wang, YH Cheng, DW Huang
US Patent 10,776,551, 2020
32020
Method, device and computer program product for integrated circuit layout generation
CM Ho, ARB Rao, MK Hsu, K Chang, KY Su, WH Chen, HS Lee
US Patent 10,140,407, 2018
32018
Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit
MK Hsu, YW Chang, TC Chen
US Patent 8,261,223, 2012
32012
Method of analyzing and detecting critical cells
A Verma, MK Hsu, CW Chang
US Patent 11,288,436, 2022
22022
Method and system of generating a layout diagram
MK Hsu, SH Chen, WK Mak, TC Wang, YH Cheng, DW Huang
US Patent 11,062,076, 2021
22021
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