| FRAIGs: A unifying representation for logic synthesis and verification A Mishchenko, S Chatterjee, R Jiang, RK Brayton ERL Technical Report, 2005 | 201 | 2005 |
| Unified QBF certification and its applications V Balabanov, JHR Jiang Formal Methods in System Design 41 (1), 45-65, 2012 | 165 | 2012 |
| Scalable don't-care-based logic optimization and resynthesis A Mishchenko, R Brayton, JHR Jiang, S Jang ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (4), 1-23, 2011 | 138 | 2011 |
| QBF resolution systems and their proof complexities V Balabanov, M Widl, JHR Jiang International Conference on Theory and Applications of Satisfiability …, 2014 | 86 | 2014 |
| Scalable exploration of functional dependency by interpolation and incremental SAT solving CC Lee, JHR Jiang, CY Huang, A Mishchenko 2007 IEEE/ACM International Conference on Computer-Aided Design, 227-233, 2007 | 78 | 2007 |
| Mvsis M Gao, JH Jiang, Y Jiang, Y Li, S Sinha, R Brayton Proc. of the Intl. Workshop on Logic Synthesis, 2001 | 68 | 2001 |
| Henkin quantifiers and Boolean formulae: A certification perspective of DQBF V Balabanov, HJK Chiang, JHR Jiang Theoretical Computer Science 523, 86-100, 2014 | 59 | 2014 |
| Bi-decomposing large Boolean functions via interpolation and satisfiability solving RR Lee, JHR Jiang, WL Hung Proceedings of the 45th annual Design Automation Conference, 636-641, 2008 | 58 | 2008 |
| Interpolating functions from large Boolean relations JHR Jiang, HP Lin, WL Hung Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 54 | 2009 |
| Optimization of Multi-Valued Multi-Level Networks GJ Jiang, M Gao, J Jiang, Y Jiang, Y Li, A Mishchenko, S Sinha, T Villa, ... | 51* | 2002 |
| Quantifier elimination via functional composition JHR Jiang Computer Aided Verification: 21st International Conference, CAV 2009 …, 2009 | 50 | 2009 |
| When Boolean satisfiability meets Gaussian elimination in a simplex way CS Han, JHR Jiang Computer Aided Verification: 24th International Conference, CAV 2012 …, 2012 | 49 | 2012 |
| A robust functional ECO engine by SAT proof minimization and interpolation techniques BH Wu, CJ Yang, CY Huang, JHR Jiang 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 729-734, 2010 | 49 | 2010 |
| String analysis via automata manipulation with logic circuit representation HE Wang, TL Tsai, CH Lin, F Yu, JHR Jiang Computer Aided Verification: 28th International Conference, CAV 2016 …, 2016 | 48 | 2016 |
| SAT-based logic optimization and resynthesis RK Brayton, JHR Jiang, S Jang Proc. of International Workshop on Logic Synthesis, 358-364, 2007 | 48 | 2007 |
| Retiming and resynthesis: A complexity perspective JHR Jiang, RK Brayton IEEE transactions on computer-aided design of integrated circuits and …, 2006 | 48 | 2006 |
| Functional dependency for verification reduction JHR Jiang, RK Brayton Computer Aided Verification: 16th International Conference, CAV 2004, Boston …, 2004 | 43 | 2004 |
| On the verification of sequential equivalence JHR Jiang, RK Brayton IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 41 | 2003 |
| Resolution proofs and Skolem functions in QBF evaluation and applications V Balabanov, JHR Jiang Computer Aided Verification: 23rd International Conference, CAV 2011 …, 2011 | 40 | 2011 |
| Logic synthesis meets machine learning: Trading exactness for generalization S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 38 | 2021 |
Valeriy BalabanovTwo SigmaVerified email at twosigma.com
